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AstroSDR

Description

Rincon Research’s AstroSDR is a complete RF payload: software-defined radio (SDR), FPGA signal processor, ARM processor, and data storage. AstroSDR combines state-of-the-art capabilities with a flexible design, resulting in a compact, efficient solution for multiple mission requirements.

High-bandwidth cross-links, command and telemetry links, store-and-forward RF collection, data compression, and digital signal processing (DSP) in a field-programmable gate array (FPGA) are all achievable with AstroSDR.

AstroSDR can operate autonomously as a standalone system or as an element in a large bus. AstroSDR supports the Space Plug-and-Play Architecture (SPA) standard to allow command, control, and telemetry functions via an on-bus SPA network.

For applications that don’t require radiation-hardened, industrial parts, the commercial grade AstroSDR FPO offers additional power options at a lower cost.

For information about AstroSDR flight, see the AstroSDR Space Flight page.

Features

  • Dual receivers & transmitters, 70 MHz to 6 GHz
  • Zynq 7045 FPGA & processor system-on-chip (SoC)
  • Embedded Linux OS for reliable operation and efficient application development
  • Radiation-tolerant NAND flash for OS and FPGA configuration
  • 64 GByte eMMC flash for data storage (optional daughter card)
  • Designed for CubeSat Next-generation Bus (CNGB) and Space Plug-and-play Architecture (SPA)

Order

Orderable Part Numbers:

ASDR-RF-mc

  • m = Model (S, E, or CGF)
    • S = Flight model
    • E = Engineering model
    • CGF = Commercial model
  • c = Customization Code
    • 00 = Standard

AstroSDR has a flexible RF path, permitting installation of mission-specific filters at time of order. Contact us to develop a custom variant for your mission’s RF requirements.

ECCN is 9A515.x.

Orders may be placed via e-mail, telephone, fax, or mail.

E-mail: sales@rincon.com
Phone: 520-519-3131
Fax: 520-519-3120
Mail: Rincon Research Corporation
Attention: Sales
101 North Wilmot Road, Suite 101
Tucson, AZ 85711

WARNING: Commodities, including associated software, firmware, and technical data, offered for sale on this site are controlled for export by the U.S. Department of State under the International Traffic in Arms Regulations (ITAR) or by the Department of Commerce under the Export Administration Regulations (EAR). Purchaser is required by U.S. law to comply with these regulations. Export, re-export, and retransfer of these commodities by any means without the required licenses or other U.S. Government authorization is prohibited by U.S. law.

Technical Specifications

System-on-Chip

Xilinx Zynq 7045 FPGA and dual ARM SoC
Processor: Dual-core ARM Cortex A9 with NEON, up to 733 MHz
Memory: 512 Mbyte DDR3 RAM (w/ECC)
Storage: 2 GByte Flash for radiation-tolerant OS storage (flight model) (1 GByte Flash for commercial model)

FPGA

Kintex-7 FPGA fabric: 350k logic cells, 900 DSP slices
Memory: 1 GByte DDR3 RAM (ECC capable)
Storage: 64 GByte eMMC flash on optional daughter card designed to support >80 MByte/s

Tuning Range

RX and TX: 70 MHz to 6 GHz
Dual RX (single RX LO) / Dual TX (single TX LO)
3 input paths per RX / 1 path per TX
Locations for SMT filters and matching networks on all RF paths

ADC/DAC Resolution

12 bit

Max Bandwidth

56 MHz single, 25 MHz dual (61.44 MSPS, 30.72 MSPS)

CAN

Microcontroller connected and bus powered for SPA support. Remote On/Off capable.
9-pin nano-D connector (2x for pass-through)

Timing Signals

FPGA connected, MMCX 50 Ohm connectors
1 PPS (2.0 V to 5.0 V)
IRIG-B-DC serial timecode (2.0 V to 5.0 V)
5/10/50 MHz reference (0.1 Vpp to 3.3 Vpp, -16 dBm to 14 dBm, sine wave or square wave)

Daughter Card Interface

30 pins 1.8 V GPIO (includes 11 ADC channels), 24 pins 3.3 V GPIO.
(Samtec LSHM-130 60-pin strip available for connections to custom board or cables)

LVDS

FPGA connected, 4 LVDS pairs, up to 200 MHz operation
9-pin nano-D connector
Supports HDLC (transmit only)
Supports SpaceWire link layer

Development Interface

External Watch Dog Timer Input, Reset, JTAG, UART console.
15-pin nano-D connector

Operating Temperature

-40°C to 85°C (flight)
0°C to 85°C (engineering and commercial - wider range available upon request)

Vibration Test

Passed GEVS proto-qualification levels

Thermal Vacuum Test

Passed CNGB spec -20°C to +50°C operational

Radiation

Projected radiation performance report available upon request

Power

CNGB compliant, 7 VDC to 13 VDC

Standby

18 mW (typ)

System Management

3.5 W (no FPGA load, ARM booted)

Idle

4 W (typ)

Passive Collect

5.5 W (typ - includes recording to flash)

23 MBaud Demod

11 W (est.)

Max

30 W

Dimensions

90 mm x 90 mm (3.543” x 3.543”)

Mass

Approximately 95 grams (without heatsink or optional daughter card) (90 grams for commercial model)